Ex parte WEINER - Page 3




                Appeal No. 1998-1615                                                                                                     
                Application 08/548,928                                                                                                   


                                                              Discussion                                                                 

                        The claims on appeal are directed to a method for producing a silicon doping test structure.                     

                Claim 1 recites an improvement in a method for making a silicon doping test structure having at least                    

                one contact which comprises the step of providing a patterned overlayer of a laser light reflective                      

                material having holes in alignment with the contact and with regions of the silicon to be doped.  The                    

                processes of claims 8 and 17 include the steps of providing an undoped silicon device having at least                    

                one contact, depositing an oxide layer on the silicon device, depositing a laser light reflective material               

                overlayer on the oxide layer, and patterning the overlayer to form openings in at least the underlying                   

                silicon regions to be doped.  According to appellant, the silicon doping test structure monitors                         

                uniformity during silicon doping, provides means for determining uniformity of both junction depth and                   

                impurity dose in a silicon wafer, and enables measurement, in real time, of the active impurity dose and                 

                junction depth of doped junctions.  See Specification, p. 2.                                                             

                        Sasaki discloses a method for producing a MOS FET type semiconductor device comprising                           

                the following steps (col. 3, line 9-col. 4, line 36; Figures 2 and 3):                                                   

                        (1)     Oxidizing a silicon semiconductor substrate 11 by a conventional thermal oxidation                       
                method using a silicon nitride layer mask to form a field insulating layer 12 of silicon dioxide;                        

                        (2)     Removing the mask and oxidizing the silicon substrate 11 by the conventional thermal                     
                oxidation method to form a gate insulating layer 13 of silicon dioxide;                                                  


                        (3)     Forming an aluminum layer on the gate insulating layer 13 and on the field insulating                    

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