Ex parte WEINER - Page 4




                Appeal No. 1998-1615                                                                                                     
                Application 08/548,928                                                                                                   


                layer 12 by a conventional vapor depositing method;                                                                      

                        (4)     Selectively removing the aluminum layer by a photoetching method to form a gate                          
                electrode 14;                                                                                                            

                        (5)     Introducing donor impurities into the silicon substrate 11 through the gate insulating                   
                layer 13 by a conventional ion-implantation method to form doped regions 15 and 16;                                      

                        (6)     Annealing the doped regions 15 and 16 with a laser beam;                                                 

                        (7)     Forming an insulating layer 17 of, for example, phosphosilicate glass, by a conventional                 
                chemical vapor deposition method;                                                                                        

                        (8)     Selectively etching the insulating layer 17 and the gate insulating layer 13 by a                        
                photoetching method to form contact holes on the doped regions 15 and 16 and on the gate electrode                       
                14;                                                                                                                      

                        (9)     Forming a conductive layer of, for example, aluminum, on the insulating layer 17 by a                    
                vapor deposition method; and                                                                                             

                        (10)    Patterning the conductive layer by a photoetching method to form interconnection lines                   
                for drain, gate and source 18a, 18b and 18c.                                                                             

                        Ishida discloses a method for forming shallow junctions in semiconductor devices using gas                       

                immersion laser doping.  Specifically, the method includes the following steps:                                          

                        (1)     masking the surface of a semiconductor wafer with a reflective material such as                          
                aluminum;                                                                                                                

                        (2)     immersing the semiconductor wafer in an atmosphere containing a dopant; and                              

                        (3)     irradiating the semiconductor wafer with a laser beam.                                                   

                        Appellant argues that "Sasaki is totally devoid of any teaching relating to a silicon doping test                


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