Appeal No. 1998-1657 Page 3
Application No. 08/674,282
corresponding to a bit line pair within the memory,
the arrangement comprising:
a sense amplifier latch configured to develop
voltages on a pair of latch nodes, said voltages
corresponding to signals on said bit line pair in
connection with a read operation;
first and second local sense amplifier drive
transistors connected respectively to provide
selectively first and second power supply voltages
to said latch;
a local column read amplifier and a pair of data
read lines coupled thereto,
said read amplifier including means responsively
coupled to at least one of said latch nodes for
developing a differential signal on said pair of
data read lines, said differential signal being
based on the state of at least one of said latch
nodes.
The references relied on in rejecting the claims follow:
U.S. Patent Application 08/684,328 ('328
Application)
(filed July 17, 1996)
U.S. Patent Application 08/284,183 ('183 Application)
(filed Aug. 2, 1994)
Young 5,247,479 Sep. 21, 1993
(filed May 23, 1991)
Toshiba et al. (Toshiba), European Patent
Application 0 175 880 Apr. 2, 1986.
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