Ex parte REYNOLDS - Page 2




          Appeal No. 1998-3024                                                        
          Application No. 08/464,298                                                  


               The disclosed invention relates to a CMOS distribution                 
          system and method.                                                          
               Claim 4 is illustrative of the claimed invention, and it               
          reads as follows:                                                           
               4.   A CMOS distribution system with means for                         
          efficiently merging two synchronized data signals comprising:               
               a first clocked CMOS signal source having an output;                   
               first clock means producing first clock pulses and                     
          coupled to said first signal source to activate said first                  
          signal source at the times of occurrence of said first clock                
          pulses;                                                                     
               a second clocked CMOS signal source and having an output               
          synchronized with the output of said first clocked CMOS signal              
          source;                                                                     
               second clock means producing second clock pulses                       
          synchronized with and occurring at times complementary to said              
          first clock pulses;                                                         
               means coupling said second clock pulses to said second                 
          signal source to activate said second signal source at the                  
          times of occurrence of said second clock pulses;                            
               first and second transmission gates having inputs and                  
          outputs with the inputs coupled to the outputs of said first                
          and second signal sources respectively;                                     
               first phase-shifting means coupled to said first clock                 
          means to produce third clock pulses phase-shifted by at least               
          approximately 90°;                                                          
               means to couple said third clock pulses to said first                  
          transmission gate to activate said first gate at the times of               
          occurrence of said third clock pulses;                                      
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