Appeal No. 1998-3024
Application No. 08/464,298
According to the examiner (Answer, page 4), “the prior
art Fig. 1 fails to show that the clock signals provided to
the gates 18 and 20 are delayed signals of the clock signals
to the first and second signal sources 10-12 as required by
claims 4 and 7.” For such a teaching, the examiner turns to
Archer which “teaches in Fig. 1 that a clock signal to a
signal source B can be provided to a transmission gate 3 after
a certain delay to protect ‘against the flip-flops
synchronizing in an unstable state due to the critical period
of the sampling edge of the clock pulse’” (Answer, page 4).
In view of the teachings of Archer, the examiner concludes
that it would have been obvious to the skilled artisan “to use
the delay circuit T of Archer at the output of each clock
means 14 and 16 of the prior art Fig. 1 in order to delay each
output to thereby protect ‘against the flip-flops
synchronizing in an unstable state’ and enable ‘the output
information of the flip-flop only after a time T after which
the probability of being in an unstable state is acceptable’”
(Answer, page 5).
Appellant argues inter alia that claims 4 and 7 recite
“first and second phase-shifting means to develop phase-
4
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007