Appeal No. 1998-3035
Application No. 08/580,036
Appellants assert at pages 1 and 2 of the specification that,
by eliminating the traditional approach of inverted feedback
paths, high speed complementary clock signals can be generated
having a low skew characteristic.
Claim 1 is illustrative of the invention and reads as
follows:
1. A method for generating dual-phase clock signals,
comprising the steps of:
generating a first clock signal by a first circuit having
a first output;
generating a second clock signal by a second circuit
having a second output;
establishing an out-of-phase relationship of about 180
degrees, between said first clock signal and said second clock
signal, by a third circuit coupled between the first output
and second output.
The Examiner relies on the following prior art:
Yoshizawa 59-97222 Jun. 05,
1984
(Published Japanese patent application)
Nagasaki et al. (Nagasaki) 1 1-117516 May 10, 1989
(Published Japanese patent application)
Claims 1-26 stand rejected as being based on an
inadequate disclosure under the first paragraph of 35 U.S.C. §
1Translations of Nagasaki and Yoshizawa accompany this
decision.
2
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