Appeal No. 1998-0706
Application 08/166,279
the interface means of each of the multiprocessor groups
including first circuit means for communicating all data
received from the link means to the interprocessor bus in the
form of a message, second circuit means for retrieving and
storing messages communicated on the interprocessor bus having
information identifying the destination processor unit as not
being a one of the plurality of processor units of that
multiprocessor group, and third circuit means for transmitting
the messages from the second circuit means onto the link means
in the form of data; and
configuration means for determining which processor unit
is located with which multiprocessor group of processor units.
17. A multiprocessor system, comprising:
at least three processor sections, each of the processor
sections containing a plurality of processor means;
link means interconnecting the three processor sections
in a ring configuration for communicating data therebetween;
each of the processor sections including,
interprocessor bus means for communicating
message data between the plurality of processor
means, the message data having identification data
indicative of a destination processor means of said
message data;
data interconnect means having right and left
data transfer means respectively coupled by the link
means to each of the other of the three processor
sections and to the interprocessor bus means for
communicating message data between the plurality of
processor means of said processor sections and the
plurality of processor means of other of the three
processor sections, the right and left data transfer
means each respectively coupled to a one and another
of the processor sections, and including routing
table means containing information indicative of the
processor section nearest the left or the right data
transfer means.
C. The references and rejections
- 3 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007