Appeal No. 1998-2925
Application 08/532,861
illustrative:
1. A method for fabricating an integrated circuit,
comprising:
providing an opening to an active region of a
semiconductor substrate upper surface;
constructing a conductive gate across a portion of said
active region; and
implanting only indium ions through said opening into
said active region, wherein said implanting forms p-type
source and drain regions within said active region
simultaneously with indium within said conductive gate.
11. A method for reducing diffusion of p-type dopant
from a patterned semiconductor gate conductor to an underlying
channel region, the method comprising:
providing a semiconductor n-type substrate and a first
layer of dielectric material across an upper surface of the
substrate;
providing a conductive material across the dielectric
material;
selectively removing a portion of the conductive material
and underlying dielectric material to present a source region,
a drain region and a patterned conductive gate having an
exposed upper surface and a lower surface adjacent the
dielectric material, said source and drain regions are spaced
apart within said substrate by a channel region underlying the
patterned conductive gate;
implanting indium into the conductive gate via the
exposed surface to a concentration peak density at a first
depth relative to the upper surface of said conductive gate,
wherein said implanting indium step further comprises
2
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