Appeal No. 1998-2966
Application 08/605,566
contact portion between the semiconductor and metal due to the
difference in energy level" (col. 1, lines 53-58). Higuchi
overcomes this problem by providing a multilayer interconnection
layer including a conductive silicon layer 6 containing
impurities such as phosphorus, arsenic, or boron (col. 6,
lines 46-50), a barrier metal layer 7 contacting the conductive
silicon layer 6, and a metal wiring layer 8 contacting the
barrier metal layer 7 (col. 6, lines 37-67). The use of a
conductive silicon layer between the conductive region having the
semiconductor property and the metal wiring layer is said to
minimize the resistance and Shottky barrier (col. 7,
lines 16-29). The multilayer interconnection layer 6/7/8 is
disclosed in several different embodiments (e.g., figures 1, 4,
7. 9, and 13); however, none of the embodiments are to a
non-volatile semiconductor memory device having a floating gate
electrode that might have the problem of impurity ion invasion.
In the final rejection, the Examiner concluded (FR4-5):
Higuchi ('971) teaches the concept [of including an
impurity introduction conductive layer in the contact hole],
such that it would have been obvious to one having ordinary
skill in the art at the time of the invention to include
[sic, provide] the memory device of the admitted prior art
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