Appeal No. 1999-1796
Application 08/705,149
BACKGROUND
The disclosed invention relates to a semiconductor having
dynamic memory, such as a dynamic random access memory (DRAM)
device, that includes a self refresh test mode in which self
refresh operations are monitored and/or modified by an
external testing device.
Claim 1 is reproduced below.
1. A semiconductor device comprising:
an interface for receiving self refresh test control
signals
from an external device;
a memory array;
a self refresh test mode controller coupled to the
interface
for outputting internal test control signals in
response to the self refresh test control signals
during a self refresh test mode of the semiconductor
device;
self refresh circuitry coupled to the self refresh test
mode
controller for producing refresh signals including
preliminary refresh signals and location refresh
signals in response to the internal test control
signals during the self refresh test mode, with at
least some of the preliminary refresh signals being
used in producing the location refresh signals; and
selection circuitry coupled to the self refresh circuitry
and the memory array for selecting memory locations
within the memory array to be refreshed in response
to the location refresh signals.
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