Appeal No. 1999-1796
Application 08/705,149
C&S&, W&"(EA4). Elements 22 and 24 do form "self refresh&A
circuitry." However, refresh control signal element 22 only
generates the MRFSH signal and element 24 only generates
internal address signals Q -Q ; they do not generate R&A&S&,
0 n-1
C&S&, W& signals as stated by the Examiner. The internal&A
address signals Q -Q from the refresh address counter 24 to
0 n-1
the row address buffer 17 are "preliminary refresh signals,"
see specification, p. 12, lines 16-19, but the Examiner does
not make this finding. The Examiner finds that "location
refresh signals" read on MRFSH and Q -Q (EA4, two places in
0 n-1
claim). However, MRFSH and Q -Q are properly "preliminary
0 n-1
refresh signals" and the signals at the output of the row
decoder can be considered "location refresh signals," see
specification, p. 12, lines 19-21. We agree that refresh
address test circuit 30 receives (indirectly) control signals
from the interface (control signal generator 20).
Importantly, the Examiner fails to address the most
significant, distinguishing limitation of claim 30: "a self
refresh test mode controller . . . for receiving control
signals from the interface and, in response thereto, modifying
self refreshing operations of the semiconductor device while
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