Appeal No. 1999-2286 Page 2
Application No. 08/352,660
second cycle is used for arbitration; and the third cycle is
used for a response.
The appellant seeks to reduce the number of clock cycles
used to access a common bus. Using an asymmetrical protocol,
the first, i.e., priority, subsystem has a zero latency in
accessing the bus, while the second subsystem must wait at
least one clock cycle after the first subsystem relinquishes
control of the bus. More specifically, the first subsystem
transmits both a request to transmit data and data
substantially simultaneously. Thereafter, the second
subsystem is granted access to the bus one cycle after
requesting access to the bus after the first subsystem has
completed its transmission. Similarly, the first subsystem
regains control of the bus one cycle after requesting access
to the bus after the second subsystem has completed its
transmission.
Claim 7, which is representative for present purposes,
follows:
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