Appeal No. 1999-2286 Page 4
Application No. 08/352,660
Rather than reiterate the arguments of the appellant or
examiner in toto, we refer the reader to the briefs and
answers for the respective details thereof.
OPINION
After considering the record, we are persuaded that the
examiner erred in rejecting claims 1-7, 9, and 10.
Accordingly, we reverse. We begin by summarizing the
examiner's rejection and the appellant‘s argument.
The examiner asserts that Nakada’s "processor 1 would
transmit the data to the processor 2 via the bus and also
request the processor 2 to transmit the data back by using the
BREQ (bus request) substantially simultaneously (see page 440-
441 and fig. 1)." (Supplemental Examiner’s Answer at 2.) The
appellant argues, "[t]he first processor does not transmit a
request to use the bus simultaneously with the data to be
transmitted." (Reply Br. at 4.)
Claims 1-6 specify in pertinent part the following
limitations: "allowing said first subsystem to transmit said
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