Appeal No. 1999-2286 Page 6
Application No. 08/352,660
to use the bus, it activates BREQ to ask Processor 2 to
release the bus.” P. 441. The request, however, is not
transmitted substantially simultaneously with data to be
transmitted on the bus. To the contrary, after activating
BREQ, Processor 1 must wait for Processor 2 to complete its
transmission before beginning to transmit data. Specifically,
“[w]hen BREQ is activated, Processor 2 releases the bus and
deactivates HOLD after completing the current outstanding bus
operations.” Id.
Relying on Craft to teach that “bus arbitration grants
the control of the shared bus to the bus masters or other
requesters having the highest priority,” (Examiner's Answer
at 3), and May to teach “a clock signal ... coupled to the
first and second subsystems ... for providing synchronization
between the subsystems,” (id. at 6), the examiner fails to
allege, let alone show, that the additional references cure
the defect of Nakada. Because the latter reference’s
Processor 1 must wait for Processor 2 to complete its
transmission before beginning to transmit data, we are not
persuaded that the teachings from the applied prior art would
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