Appeal No. 1999-2571
Application No. 08/820,200
Claims 1, 3, 5 through 11, and 13 through 19 stand
rejected under 35 U.S.C. § 103 as being unpatentable over
Sharma in view of McCarthy.1
Reference is made to the Examiner's Answer (Paper No. 6,
mailed April 6, 1999) for the examiner's complete reasoning in
support of the rejections, and to appellants' Brief (Paper No.
5, filed February 23, 1999) for appellants' arguments
thereagainst.
OPINION
We have carefully considered the claims, the applied
prior art references, and the respective positions articulated
by appellants and the examiner. As a consequence of our
review, we will reverse the obviousness rejection of claims 1,
3, 5 through 11, and 13 through 19.
Independent claims 1 and 19 recite the steps of
"selecting a semiconductor fabrication process for fabricating
the semiconductor device from a group of semiconductor
fabrication processes consisting of CMOS, NMOS, PMOS, Bipolar,
1The examiner (Answer, page 3) withdraws the rejection of claims 1, 3,
5 through 11, and 13 through 19 under 35 U.S.C. § 112, second paragraph.
Also, the examiner omits in the Answer the rejection of claims 1, 3, 5 through
11, and 13 through 19 under 35 U.S.C. § 103 over Sharma, McCarthy, and Sze.
Thus, only the rejection of claims 1, 3, 5 through 11, and 13 through 19 under
35 U.S.C. § 103 over Sharma and McCarthy remains before us on appeal.
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