Appeal No. 1999-2571
Application No. 08/820,200
In column 4, lines 30-34, Sharma states that the wafer is
processed "through the conventional CMOS/Bipolar process
sequence using conventional SOI device processing
technologies." Although we appreciate how the examiner read
the language used in this excerpt as suggesting CMOS or
Bipolar fabrication processes, as the language is ambiguous,
it is clear in light of the portion discussed above that
Sharma means that CMOS/Bipolar circuits are formed using SOI
processes. Accordingly, Sharma fails to disclose the steps of
choosing and using one of the recited non-SOI fabrication
processes to form a semiconductor device. As McCarthy does
not cure this deficiency, no prima facie case of obviousness
has been established, and we cannot sustain the rejection of
claims 1 and 19 nor of their dependents, claims 3, 5 through
11, and 13 through 18.
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