Appeal No. 2001-0014 Page 3
Application No. 09/070,899
hermetic enclosure with opposed walls constituted
respectively by the chip and the ceramic substrate, and
wherein electrical contact with each opto-electronic
device of the array is made by way of electrically
conductive connections at least one of which includes an
electrically conductive via extending through the
thickness of the ceramic substrate.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Chen et al. (Chen) 5,041,900 Aug. 20,
1991
VanZeghbroeck 5,600,130 Feb. 4,
1997
Sato et al. (Sato ‘419) 5,719,414 Feb. 17,
1998
Sato et al. (Sato ‘566) 5,798,566 Aug. 25, 1998
Edwards et al. (Edwards) 5,881,945 Mar.
16, 1999
(filed Apr. 30, 1997)
Claims 6 and 7 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Sato ‘566 in view of VanZeghbroeck,
Chen and Sato ‘414. Claim 8 stands rejected under 35 U.S.C. §
103 as being unpatentable over Sato ‘566, VanZeghbroeck, Chen
and Sato ‘414 in combination with Edwards. We note that
claims 6 through 8 were also rejected under 35 U.S.C. § 101
and § 112 as set forth in the final rejection (Paper No. 12,
mailed December 9, 1999), which were neither included nor
argued in the answer. We assume that these other grounds of
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