Appeal No. 1999-0853
Application No. 08/709,869
switching transition near the knees of the transfer curve
having two parallel paths. See Appellants' specification page
6, line 35 through page 7, line 31. The circuitry arrangement
has been chosen such that when the input 18 rises from low to
high, no hysteresis occurs and branch 34 is taken whereas when
the input transition changes from high to low, hysteresis
occurs and branch 33 is taken. See Appellants' Figures 2, 2A
and 2B and the specification page 8, line 26 to page 9, line
10.
Independent claim 1 is reproduced as follows:
1. A buffer circuit of the type having a chain of amplifying
circuits (10, 11, 12) connected output to input between an
input pad of a semiconductor chip and circuits that process an
input signal at the pad, the chip having two power supply
terminals, the chain including a first circuit (10) having its
output connected to the input of a second amplifying circuit,
the second circuit having an input and an output, the transfer
curve for the switching operation of the first circuit having
high and low substantially constant output levels (30, 31)
representing binary logic values in response to the input
signal and having a steep transition between the high and low
output levels and having hysteresis wherein the transition has
parallel paths at one knee joining a constant part of the
curve to the transition part of the transfer curve, wherein
the improvement comprises,
an FET (23 or 36) connected to conduct between the output
of the first circuit and one of the power supply terminals in
response to a gate signal from an output (15) of a circuit
(12) in the chain to form a feedback loop,
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: November 3, 2007