Appeal No. 1999-0853
Application No. 08/709,869
with the Examiner that Shimizu's circuit includes inverters
10, 11 & 12 wherein the output 16 from inverter 10 is
connected to the drain 25 of the FET 23, the output 15 from
the delay inverters 11 and 12 is connected to the gate 27 and
the power supply or ground is connected to the source 26.
However, we cannot look at a limited portion of the
circuitry in a vacuum but rather need to analyze the circuit
as a whole. We find that Shimizu teaches additional circuitry
in which a FET 9 and a ground 12 are connected to the FET 10
via 10S and 10G to compliment the FET 10 (see Shimizu page 6,
lines 15-17). This arrangement would certainly affect the
operation of FET 10. We are invited by the Examiner to
speculate, without further evidence, that the Shimizu FET 10
would inherently provide the same hysteresis operation as
claimed by Appellants. We cannot do so.
Further, we find that claims 2 through 8 are dependent on
claim 1 and thereby recite the above limitation. Furthermore,
we note that claim 9 also includes the above limitation found
in claim 1. Therefore, we find that Shimizu fails to teach
all of the limitations of claims 1 through 9, and thereby
these claims are not anticipated by Shimizu.
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