Appeal No. 1999-2347
Application 08/892,560
Wolf, Silicon Processing for the VLSI Era ) Volume 2:
Process Integration (Lattice Press 1990), pp. 190-194.
The main references to Barber, Erie, and Kim are summarized
below.
Barber discloses a process for making borderless contacts
through an insulating region. A silicon nitride layer 18 is
deposited over diffusion region 12, field oxide region 14, and
polysilicon interconnect line 16, where 12 and 16 are conductive
regions. A layer 20 of borophosphosilicate glass (BPSG) is
deposited over the layer 18. Contact windows (vias) are etched
in three steps (col. 3, lines 15-25): (1) removing moisture from
a reactive ion etch chamber; (2) etching the BPSG 20 until the
silicon nitride layer 19 is exposed; and (3) removing the
remainder of the silicon nitride layer 18 exposing the conductive
regions. The purpose of the etch stop layer is to prevent
consumption of the field oxide and to prevent removal of the
conduction regions. Barber does not mention the problem of
non-conductive back-sputtered compounds.
Erie discloses a process for making oversized vias in
multilayer metallization structures (e.g., col. 1, lines 11-15;
col. 2, lines 41-43). A thin film dielectric barrier material 18
of titanium oxide (TixOy) or some other material (col. 4,
lines 5-7) is deposited over metallization interconnects 13, and
a dielectric layer 19 of silicon dioxide is deposited over
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