Appeal No. 2001-1814
Application 09/092,115
in conjunction with interconnects or gate tops with linewidth as
provided by the lithography. This method allows the typically
smallest linewidth (the gate length) to be sublithographic in
conjunction with standard lithography.
Representative claim 1 is reproduced as follows:
1. A method of fabrication of an integrated circuit,
comprising the steps of:
(a) patterning a first layer of resist on a layer of gate
material to define gate locations;
(b) reducing the linewidth of said patterned layer of
resist of step (a);
(c) using said reduced linewidth patterned resist as an
etch mask to form gates from said layer of gate material;
(d) forming a layer of dielectric on said gates;
(e) patterning a second layer of photoresist to define
interconnects;
(f) using said patterned photoresist without linewidth
reduction to form interconnects over said gates.
The examiner relies on the following references:
Auda et al. (Auda) 5,139,904 Aug. 18, 1992
Maniar et al. (Maniar) 5,525,542 June 11, 1996
Mishra et al. (Mishra) 5,798,555 Aug. 25, 1998
(filed Nov. 27, 1996)
S. Wolf, “Silicon Processing for the VLSI Era Volume 2 - Process
Integration,” 1986, pages 278-286.
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