Appeal No. 2001-1814
Application 09/092,115
there is no need to reduce the linewidth of interconnect areas of
the circuit, the artisan would have employed standard etching
techniques which would yield unreduced linewidth patterns. Thus,
the examiner finds that it would have been obvious to the artisan
to use reduced linewidth patterns on the gates as taught by Auda
but to use conventional linewidth lithography on the
interconnects as taught by Wolf [answer, pages 3-5].
Appellants argue that Auda would inherently use the same
photoresist linewidth reduction to the interconnect formation as
to the gate formation. In other words, appellants argue that the
applied prior art fails to teach the use of both reduced and
nonreduced linewidths [brief, page 3].
The examiner responds that Wolf shows that linewidths of
the gate electrode and the CVD tungsten interconnect are
different. The examiner asserts that the use of a reduced
linewidth would not be necessary in the formation of the CVD
tungsten interconnect as compared to the gate electrode in Wolf’s
Figure 4-58. The examiner notes that the applied prior art only
teaches a reduced linewidth for the gate electrodes [answer, page
7].
We will sustain the examiner’s rejection of claims 1-3.
Appellants’ argument that Auda would inherently apply the same
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