Appeal No. 2001-1814
Application 09/092,115
examiner responds that Auda suggests the use of reduced
photoresist in forming short channel polysilicon gate FETs but
does not suggest this technique in the formation of the
conventional interconnects. The examiner notes that it would be
implausible to use reduced photoresist for conventional
interconnects without any explicit motivation [answer, pages 7-
8].
We will sustain the examiner’s rejection of claim 4. We
are not persuaded by appellants’ argument that the applied
references are inconsistent. The examiner is using Auda as
motivation to reduce the gate linewidth of Mishra for the
advantages disclosed by Auda. We agree with the examiner’s
argument that Auda only teaches linewidth reduction with respect
to the gate and does not suggest such reduction for the
interconnects as well.
In summary, we have sustained the examiner’s rejection of
each of the claims on appeal. Therefore, the decision of the
examiner rejecting claims 1-4 is affirmed.
-8-
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