Appeal No. 2001-1814
Application 09/092,115
photoresist linewidth reduction to the interconnect formation as
to the gate is not convincing. Auda teaches the use of linewidth
reduction in the formation of FET gates because it permits the
miniaturization of such FET devices. We agree with the examiner,
however, that similar linewidth reduction is not necessary in
forming interconnect lines between components. There is no
reason why the artisan would go to the extra effort of reducing
linewidths where such reduction serves no specific purpose. The
collective teachings of the applied prior art teach that the
linewidths resulting from conventional lithography should be
reduced in the formation of gates. There is no similar teaching
that the formation of interconnects should have similarly reduced
linewidths. Appellants’ argument that there is no suggestion of
using reduced and nonreduced linewidths in the same device is,
therefore, not persuasive.
We now consider the rejection of claim 4 based on the
teachings of Mishra, Auda and Maniar. The examiner’s rejection
is explained on pages 5-6 of the answer. Appellants again argue
that the references have no suggestion of the mixed use of
photoresist with and without linewidth reduction. Appellants
argue that Mishra is inconsistent with Auda and the references
fail to suggest the claimed combination [brief, pages 3-4]. The
-7-
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007