Appeal No. 2001-2164
Application No. 09/024,620
Representative independent claim 1 is reproduced as follows:
1. A method of improving memory latency associated with a
read-type operation in a multi-processor computer system having a
plurality of processing units, each processing unit further
having an associated cache, the method comprising the steps of:
a requesting processing unit issuing a message to an
interconnect of the computer system, indicating that the
requesting processing unit desires to read a value from an
address of a memory device of the computer system;
each cache snooping the interconnect to detect the message;
each cache transmitting a response to the message, wherein a
tagged intervention response is transmitted from a responding
cache to indicate (i) that the responding cache contains a
modified value corresponding to the address of the memory device
that has not been written to the memory device, (ii) that the
responding cache shares the modified value with at least one
other cache of an adjacent processing unit, and (iii) that the
responding cache will exclusively source the value;
associating a priority with each response from each cache;
detecting each response and its associated priority; and
forwarding a response with a highest priority to the
requesting processing unit.
The examiner relies on the following references:
Wilson, Jr. et al. (Wilson) 4,755,930 Jul. 5, 1988
Singh et al. (Singh) 5,903,908 May 11, 1999
(filed Oct. 15, 1996)
Claims 1-20 stand rejected under 35 U.S.C. § 103 as
unpatentable over Singh and Wilson.
-3–
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