Appeal No. 2001-2164
Application No. 09/024,620
“shares” a value with other caches.
The instant claims require not only that the cache “share” a
value with other caches, but that that shared value be a modified
value. Accordingly, the tagged intervention response is provided
only by a responding cache holding requested data that are both
shared and modified.
We find nothing in Singh indicating that the requested data
held by a responding cache is “modified,” i.e., the value held
has not been written to system memory. In fact, every indication
in Singh is that the data in the responding caches is consistent
with that in the system memory. Column 7, lines 60 et seq., of
Singh states that the processor accesses from the instruction
fetch unit “are always fetch operations with no intent to modify
the data...” Column 8, lines 21-25, of Singh indicates that the
processor may update any portion of the cache line it chooses,
resulting in a “write command being issued to the data cache
memory...with the modified data and the data cache
memory...updates its copy of the cache line to reflect the
change,” but this does not indicate that the data in the cache
memory is different, or inconsistent, from the data in the system
memory. In fact, it appears to indicate that the data in the
-9–
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