Appeal No. 2001-2448
Application No. 09/105,492
BACKGROUND
Appellants’ invention is directed to a decoding system that
uses a memory arbitration scheme to combine the speed and
responsiveness of hardware with the flexibility and efficiency of
software and to improve the decoding system performance
(specification, page 14). Dedicated logic devices issue “GO
signals” for memory access which are fed into a first-in, first-
out (FIFO) queue (specification, pages 16 & 17). Dequeue logic
receives memory ready signals and asserts a DEQUEUE signal if the
memory device is idle and therefore ready to handle a memory
transaction (specification, page 17).
Representative independent claim 1 is reproduced as follows:
1. A decoding system comprising:
a memory storage device that stores data;
a plurality of decoding devices coupled to said memory
storage device and which carry out memory transactions with the
memory storage device;
a microcontroller coupled to said memory storage device and
to said plurality of decoding devices, comprising:
a control logic device that issues a primary GO
instruction associated with one of said decoding devices;
and
a FIFO that queues the primary GO instruction,
2
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