Appeal No. 2001-2448
Application No. 09/105,492
not stored in a queue or dequeued therefrom and are, in fact,
used to control the operation of the queue (id.).
In response to Appellants’ arguments, the Examiner asserts
that Kavipurapu’s elements 201, 203 and 205 are memory devices
and inherently contain decoding circuitry (answer, page 9). The
Examiner also points out that, since specific kinds of decoding
devices and the memory transactions are not claimed, the
operation of these elements of Kavipurapu in relation to the line
cache 206 are characterized as “memory transactions” (answer,
page 10). Furthermore, the Examiner relies on the teaching of
the prior art that the request queue 202 operates in a FIFO
manner (col. 9, lines 58-62) and concludes that the WRITE and
SEARCH commands of Kavipurapu are put in the request queue which
are dequeued in response to a control signal (answer, page 10).
Before addressing the Examiner’s rejection based on prior
art, it is essential that we understand the claimed subject
matter and determine its scope. Accordingly, we will initially
direct our attention to Appellants’ claim 1 in order to determine
its scope. Claim interpretation must begin with the language of
the claim itself. See Smithkline Diagnostics, Inc. v. Helena
Laboratories Corp., 859 F.2d 878, 882, 8 USPQ2d 1468, 1472 (Fed.
Cir. 1988). See also Pitney Bowes, Inc. v. Hewlett-Packard Co.,
4
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