Appeal No. 2001-2448
Application No. 09/105,492
182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999) (“The
starting point for any claim construction must be the claims
themselves.”).
A review of claim 1 reveals that it is the primary GO
instruction issued by the recited microcontroller that the
claimed FIFO queues not the memory transaction requests issued by
the recited decoding devices. Once the memory transaction is
performed and one of the decoding devices accesses the memory
storage, the FIFO further dequeues the primary GO instruction.
Therefore, the FIFO queues and dequeues the memory grant signals
or the GO instructions. Similarly, claims 7 and 13 require that
the memory arbitration queue memory grant signals and dequeue a
grant when a decoding device is to perform a memory transaction.
A rejection for anticipation under section 102 requires that
each and every limitation of the claimed invention be disclosed
in a single prior art reference. In re Paulsen, 30 F.3d 1475,
1478-79, 31 USPQ2d 1671, 1673 (Fed. Cir. 1994). See also Atlas
Powder Co. v. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943,
1947 (Fed. Cir. 1999).
We observe that Kavipurapu, as depicted in figure 20,
teaches that request queue 202 operates in a FIFO manner (col. 9,
lines 58-62), but provides no disclosure related to memory grant
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