Appeal No. 2001-2448
Application No. 09/105,492
wherein said one of said decoding devices accesses said
memory storage device if the primary GO instruction is
dequeued from said FIFO.
The Examiner relies on the following reference in rejecting
the claims:
Kavipurapu 6,009,488 Dec. 28, 1999
(filed Nov. 7, 1997)
Claims 1-20 stand rejected under 35 U.S.C. § 102(e) as being
anticipated by Kavipurapu.
We make reference to the answer (Paper No. 16, mailed May 7,
2001) for the Examiner’s reasoning in support of the rejection,
and to the appeal brief (Paper No. 15, filed March 26, 2001) for
Appellants’ arguments thereagainst.
OPINION
Appellants argue that, among the elements cited in
Kavipurapu, latch 201 is the only element that could arguably
carry out memory transactions but question the way the Examiner
characterizes other elements 201, 203, 205 as decoders that carry
out memory transactions. Appellants also contest the Examiner’s
characterization of WRITE and SEARCH commands of Kavipurapu as
the claimed GO instruction and indicate that neither command is
queued or dequeued from a FIFO (brief, page 5). Appellants
further point out that the disclosed WRITE and SEARCH signals are
3
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007