Appeal No. 2001-2448
Application No. 09/105,492
queues. Figures 20-23 actually depict the receive and transmit
link interface circuitry wherein the bus cycle of the processor
is decoded to be either a read or write as the data and address
information are latched (col. 9, lines 50-52). An appropriate
header from header pool 207 as well as the address/data/control
of the bus cycle is mapped to the packet as it is placed in
request queue 202 (col. 9, lines 52-61). Therefore, what the
Examiner takes for the queuing of the GO instructions is, in
fact, queuing of the requests wherein either data is packetized
and sent or data is sent to the memory controller for storage
(col. 10, lines 17-31).
In view of the analysis above, we find that the Examiner has
failed to meet the burden of providing a prima facie case of
anticipation since, as discussed above, the computer system of
Kavipurapu queues the requests instead of the claimed queuing and
dequeuing of the GO or the memory grant signals. Accordingly,
the rejection of claims 1, 7 and 13 as well as claims 2-6, 8-12
and 14-20, dependent thereupon, under 35 U.S.C. § 102 over
Kavipurapu cannot be sustained.
6
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007