Appeal No. 2001-2593
Application No. 09/074,197
BACKGROUND
Appellants’ invention is directed to a digital multiplier
for multiplying a plurality of multiplicands. An adder adds the
intermediate results that are generated from the multiplicands
while delay elements delay the arrival of at least one of the
intermediate signals in order to synchronize the arrival of the
signals in the adder circuit (specification, page 3).
Representative independent claim 28 is reproduced below:
28. A digital multiplier for multiplying signals and
multiplier signals to produce final result signals, comprising:
means for generating a plurality of intermediate result
signals from said multiplicand signals and from said multiplier
signals, and placing said intermediate result signals on
intermediate result signal lines;
a plurality of adder circuits receiving said intermediate
result signal lines for adding said intermediate result signals
to generate said final result signals; and
a plurality of unclocked delay elements placed in selected
intermediate result signal lines so as to delay the arrival of
some of said intermediate result signals so said adder circuits
to synchronize the arrival of the signals input to said adder
circuits and reduce spurious switching of said adder circuits.
The Examiner relies on the following references in rejecting
the claims:
Goldschmidt et al (Goldschmidt) 3,515,344 June 2, 1970
Nash 4,811,270 Mar. 7, 1989
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