Appeal No. 2001-2593
Application No. 09/074,197
page 7). Appellants point out that Nash, instead of the claimed
synchronizing the arrival of the intermediate results signals in
the adder circuit, uses a clocked delay signal (col. 5, lines 31-
37) and is concerned with delaying the adder signals by at least
one clock period (brief, page 7). Additionally, Appellants
question the Examiner’s reason for modifying Nash and using
unclocked delay elements where the reference is not concerned
with reducing spurious switching of adder circuits (id.).
The Examiner responds to Appellants’ arguments by asserting
that using unclocked delay elements in the adder of Nash would
have been obvious since such elements are well known in the art
and are used in Nash for synchronizing the inputs (answer, page
5). The Examiner further relies on the broad recitation of the
delay elements being unclocked to conclude that such kind of
delay elements are known in the art (id.).
In rejecting claims under 35 U.S.C. § 103, the Examiner
bears the initial burden of presenting a prima facie case of
obviousness. See In re Rijckaert, 9 F.3d 1531, 1532, 28 USPQ2d
1955, 1956 (Fed. Cir. 1993). To reach a conclusion of
obviousness under § 103, the examiner must produce a factual
basis supported by teaching in a prior art reference or shown to
be common knowledge of unquestionable demonstration. Our
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