Appeal No. 2001-2593
Application No. 09/074,197
reviewing court requires this evidence in order to establish a
prima facie case. In re Piasecki, 745 F.2d 1468, 1471-72, 223
USPQ 785, 787-88 (Fed. Cir. 1984). The Examiner must not only
identify the elements in the prior art, but also show “some
objective teaching in the prior art or that knowledge generally
available to one of ordinary skill in the art would lead the
individual to combine the relevant teachings of the references.”
In re Fine, 837 F.2d 1071, 1074, 5 USPQ2d 1596, 1598 (Fed. Cir.
1988).
Nash relates to a full adder circuit to be implemented in
multi-bit digital multipliers or dividers (col. 1, lines 5-9).
The multiplier includes an array of one-bit delay shift registers
19 that delay the eight-bit multiplicand and synchronize its
arrival at the next row of the full adder (col. 3, lines 19-24
and Figure 1). However, as pointed out by Appellants (brief,
page 7), Nash indicates that all of the circuit elements in
Figure 1 are clocked (col. 5, lines 31-37) which means that the
delay elements 19 are also clocked. Therefore, contrary to the
Examiner’s proposed modification of the clocked shift registers
of Nash to use unclocked delay elements, we do not find any
teaching or suggestion in Nash, nor, in Appellants’ somewhat
broad recitation of “an unclocked delay element” that supports
the obviousness of the modification. The Examiner has further
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