Appeal No. 2001-2593
Application No. 09/074,197
1, lines 41-47). However, we remain unpersuaded by the
Examiner’s assertion that the absence of the description of a
clock means that the latches are unclocked and further buttress
our view by referring to Col. 5, lines 48-53 of Goldschmidt
describing the structure of the disclosed latch registers to be
the same as those disclosed in U.S. Patent No. 3,340,388.3 A
review of Patent No. 3,340,388 shows that the shift registers
used in the adder of Goldschmidt are all clocked (col. 3, lines
33-39). As depicted in Figure 2 of Patent No. 3,340,388, the
latching function is performed by storing the carry and sum
outputs in a pair of clocked latches 30 and 40 and therefore,
what the Examiner characterizes in Goldschmidt as unclocked delay
elements, are actually clocked latch registers. Thus, since all
the limitations of the appealed claims are not taught by the
applied prior art, Goldschmidt cannot anticipate the claims.
Accordingly, the 35 U.S.C. § 102 rejection of claims 23 and 28 is
not sustained.
Turning to the 35 U.S.C. § 103 rejection of the claims,
Appellants argue that Nash does not teach that delay elements 19
are unclocked and instead, describes the delay elements as one
bit shift registers which are well-known to be clocked (brief,
3 The commonly owned U.S. Patent No. 3,340,388 to Earle, a copy of
which accompanies this decision.
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