Appeal No. 2002-1981
Application No. 09/316,580
(d) a device silicon layer overlying said first
dielectric layer, said device silicon layer having an upper
surface;
(e) a second dielectric layer on said handle die
underlying the opposite side of said silicide layer; and
(f) interconnected transistors in and at the upper
surface of said device silicon layer.
7. A silicon-on insulator integrated circuit comprising:
(a) a handle die;
(b) a first dielectric layer formed on said handle die
(c) a substantially continuous silicide layer formed on
said first dielectric layer, said silicide layer having a
controlled resistance and providing a diffusion barrier to
impurities;
(d) a substantially continuous second dielectric layer
disposed between said silicide layer and a device silicon
layer;
(e) trenches extending through said device silicon layer
and silicide layer and separating said device silicon layer
into islands each with an underlying continuous silicide area;
and
(f) interconnected transistors in and at an upper surface
of said device silicon layer.
The references relied upon by the examiner are:
Moslehi 5,102,821 Apr. 7, 1992
See et al. 5,212,397 May 18, 1993
(See)
Ochiai 5,378,919 Jan. 3, 1995
Kameyama et al. 64-73659 Mar. 17, 1989
(Kameyama)
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