Appeal No. 2002-1981
Application No. 09/316,580
Background
The invention relates to dielectrically isolated
semiconductor integrated circuits and methods of fabrication.
Specification, page 1, lines 14-16. According to appellants, the
invention provides silicon-on-insulator bonded wafer processing
which has numerous advantages over conventional processes. See
Specification, page 4, lines 12-20.
Discussion
For purposes of this appeal, appellants indicate that the
following groups of claims stand or fall together: (1) claims 1-
3, (2) claims 4-5, (3) claims 7-9, (4) claims 10, 13-15 and 22,
(5) claims 16-18 and (6) claims 19-21. Appeal brief, page 6.
1. Rejection of claims 4, 5, 10 and 13-22 under 35 U.S.C.
§ 112, first paragraph
Claims 4 and 5
Appellants argue that the subject matter of claims 4 and 5
is supported on page 7, lines 22-29 of the specification and in
Figure 4a. See examiner's answer, page 13. It is the examiner's
position that claim 1, from which these claims depend, only reads
on the structure disclosed in Figure 3 while the subject matter
of claims 4 and 5 relates to the structure disclosed in Figure 4.
5
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