Appeal No. 2003-0886
Application No. 09/466,845 Page 7
layer 34 of field oxide covers the top surface of substrate 32.
Bottom cell wordlines 36 extend over insulation layer 34 and are
physically isolated from each other by first isolation strips 38
of oxide. Bottom gate dielectric 40 of oxide covers bottom cell
wordlines 36 and first isolation strips 38. Polysilicon layer 42
completely covers bottom gate dielectric 40. Heavily doped
regions 44 are formed into thin polysilicon film 40, and serve as
conductive bitlines 44. On the bottom surface of polysilicon
film 42, channel regions of thin film bottom cell transistors 46
(figure 7B) are formed directly above bottom cell wordlines 36
and between adjacent bitlines 44. Bitlines 44 serve as the
source and drain electrodes for bottom cell memory transistors
46, whereas bottom cell wordlines 36 serve as gate electrodes for
bottom cell memory transistors 46. Top gate dielectric 48 of
oxide completely covers polysilicon layer 42 and the bitlines 44,
which have been formed into polysilicon layer 42. Conductive
polysilicon strips 50 are formed over top gate dielectric 48, and
serve as top cell wordlines (col. 7, lines 37 through col. 8,
line 8). By forming memory cell transistors on both the top and
bottom surfaces of thin film polysilicon 42 in an alternating
fashion, the MROM doubles the storage density of a conventional,
prior art MROM (col. 8, lines 37-42). From the disclosure of
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