Ex Parte SIMON et al - Page 3




                 Appeal No. 2001-1118                                                                                                               
                 Application 09/262,690                                                                                                             
                 U.S.C. § 102(b) by Chakravorty et al. (Chakravorty), U.S. Patent 5,436,504, issued 25 July 1995,                                   
                 based on application 09/064,794, filed 19 May 1993.                                                                                
                          5.      Claim 12 has been rejected as being unpatentable under 35 U.S.C. § 103 over                                       
                 Chakravorty in view of Nakajima et al. (Nakajima), U.S. Patent 5,444,302, issued 22 August                                         
                 1995, based on application 09/168,506, filed 22 December 1993.                                                                     
                          6.         Claims 15 and 18-27 have been rejected as being unpatentable under 35 U.S.C. §                                 
                 103 over Chakravorty in view of Hoshino, U.S. Patent 4,985,750, issued 15 January 1991, based                                      
                 on application 07/097,738, filed 17 September 1987.                                                                                
                          7.      The independent claims are reproduced as follows:                                                                 
                          11.     A semiconductor article comprising:                                                                               
                          a.  a material having a via;                                                                                              
                          b.  a first layer deposited in the via, the first layer lining the via;                                                   
                          c.  a second layer deposited on the first layer, the second layer is deposited using Rf                                   
                          biased sputter deposition; wherein the first layer deposited on the bottom of the via is                                  
                          substantially removed during the Rf biased sputter deposition of the second layer but                                     
                          substantially all of the first layer deposited on the sidewalls of the via during the Rf                                  
                          biased sputter deposition of the second layer is unaffected.                                                              

                          18.     A semiconductor article comprising:                                                                               
                          a.  a material having a via;                                                                                              
                          b.  a first layer deposited in the via, the first layer lining the via;                                                   

                          c.  a second liner layer deposited on the first liner layer, the second layer is deposited                                
                          using Rf biased sputter deposition; wherein the first layer deposited on the bottom of the                                
                          via is substantially removed during the Rf biased sputter deposition of the second layer                                  
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