Appeal No. 2002-0792
Application 08/801,646
Appellants’ claim 1 is representative of the claimed
invention and is reproduced as follows:
1. In a computing system having a processor, a memory and a
kernel level scheduler, wherein the processor includes a user
mode and a protected kernel mode, a method of scheduling a
plurality of threads from a multi-threaded program for execution
in user mode, wherein the multi-threaded program includes a user
level scheduler, the method comprising the steps of:
defining a shared arena within the memory, wherein the
shared arena includes a register save area for each of the
plurality of threads; and
selecting, at the user level scheduler, a thread from the
plurality of threads to be executed on the processor, wherein the
step of selecting includes the step of reading register context
associated with the selected thread from one of the plurality of
register save areas.
References
The references relied on by the Examiner are as follows:
Anderson et al. (Anderson), “Scheduler Activations: Effective
Kernel Support for the User-Level Management of Parallelism”,
Department of Computer Science and Engineering, University of
Washington, Seattle, WA, pp 95-109 (1991).
Polychronopoulos et al. (Polychronopoulos), “Nano-Threads: A
User-Level Threads Architecture”, CSRD TR 1297, 1993, pp 2-22.
Rejections at Issue
Claims 1 through 6, 13, 14, 18 through 34, 40 through 46,
and 52 through 55 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Anderson in view of Polychronopoulos.
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