Appeal No. 2002-0792
Application 08/801,646
brief. We note that Appellants’ claim 1 recites:
defining a shared arena within the memory, wherein the
shared arena includes a register save area for each of the
plurality of threads; and
selecting, at the user level scheduler, a thread from
the plurality of threads to be executed on the processor,
wherein the step of selecting includes the step of reading
context associated with the selected thread from one of the
plurality of register save areas.
We also note that Appellants’ claim 19 recites:
first program code executing in the processor for
creating a shared arena within the memory, wherein the
shared arena includes a register save area for each of the
plurality of threads; and
second program code executing in the processor, wherein
the second program code includes scheduling code for
scheduling threads from the plurality of threads, wherein
the scheduling code includes program code for selecting a
thread from the plurality of threads and for switching to
the selected thread by reading register context associated
with the selected thread from one of the plurality of
register save areas.
Appellants’ claim 23 recites:
first program code executing in one of the plurality of
processors for creating a shared arena within the memory,
wherein the shared arena includes a register save area for
each of the plurality of threads; and
second program code executing in the processor, wherein
the second program code includes scheduling code for
scheduling threads from the plurality of threads, wherein
the scheduling code includes program code for selecting a
thread from the plurality of threads and for switching to
the selected thread by reading register context associated
with the selected thread from one of the plurality of
register save areas.
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