Appeal No. 2002-0792
Application 08/801,646
allocating, at the user level scheduler, one or more
threads of the plurality of threads to each of the
processors assigned to the program, wherein the step of
allocating includes the step of reading register context
from one of the plurality of register save areas.
For the reasons as we have pointed out above, we fail to find
that Polychronopoulos or Anderson teaches the above limitations.
For claims 27, 40 and 52, Appellants argue that the Examiner
has failed to show how the references cite and teach or suggest
all the limitations recited in these claims. In particular,
Appellants argue that the Examiner has not shown how the
references teach the use of a first and second kernel of
scheduler to schedule threads across a first and second kernel.
We note that Appellants’ claim 23 recites:
a kernel level scheduler, executing within the
protected kernel mode of one of the plurality of processors,
for allocating processors to a program;
first program code executing in one of the plurality of
processors for creating a shared arena within the memory,
wherein the shared arena includes a register save area for
each of the plurality of threads; and
second program code executing in the processor, wherein
the second program code includes scheduling code for
scheduling threads from the plurality of threads, wherein
the scheduling code includes program code for selecting a
thread from the plurality of threads and for switching to
the selected thread by reading register context associated
with the selected thread from one of the plurality of
register save areas.
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