Appeal No. 2003-0142
Application No. 09/071,912
Independent claim 1 is reproduced as follows:
1. A receiving latch with hysteresis circuit for receiving data
on cross chip boundaries in a chip to chip interface, comprising
a receiver enable input pin (E), a data line (D to L1), a
receiver latch circuit section including a receiver feed section
(20, 115, 119, 120), a clock section (30) and a hysteresis latch
(40, 114,, 114' 114", 116, 116', 116", 117, 118) having a pass
gate (114), configured so that said receiver enable input pin (E)
is settable to a high (Data ON) or low (Data OFF) voltage level
to set the hysteresis for the receiver latch circuit section and
also to gate any input data at a data input pad (D) to the data
line setting the hysteresis of the receiver latch circuit section
when the voltage level at said enable input pin (E) goes high,
and wherein a clock signal is supplied by the clock section of
said receiver latch circuit section, and said receiver feed
section supplies a data line output (DN) of said receiver feed
section to the hysteresis latch having said pass gate (114), and
wherein said hysteresis latch with the pass gate has clock
couplings to a pgate and an ngate of a pass gate PFET (114') and
a pass gate NFET (114") transistor of the pass gate (114),
respectively, with the drains of said pass gate PFET (114') and
pass gate NFET (114") being coupled to ground via a hysteresis
latch NFET (118) of said hysteresis latch and with the sources of
said pass gate PFET (114') and pass gate NFET (114") coupled to
the input data line via the data line output (DN) of said
receiver feed section, the drain of a hysteresis latch PFET (117)
of said hysteresis latch having its source connected to a
positive potential and the source of said hysteresis latch
NFET (118) having its drain connected to ground and both said
hysteresis latch PFET (117) and said hysteresis latch NFET (118)
having their gate connection to a data line latch output (L1)
for gating the data line information out of the hysteresis
latch (40).
The examiner relies on the following references:
Mote, Jr. 5,324,996 Jun. 28, 1994
Yoshida 5,812,002 Sep. 22, 1998
(filed Jun. 14, 1996)
Claims 1-3 stand rejected under 35 U.S.C. § 103 as
unpatentable over Yoshida and Mote.
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