Appeal No. 2003-0142
Application No. 09/071,912
These showings by the examiner are an essential part of complying
with the burden of presenting a prima facie case of obviousness.
Note In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444
(Fed. Cir. 1992). If that burden is met, the burden then shifts
to the applicant to overcome the prima facie case with argument
and/or evidence. Obviousness is then determined on the basis of
the evidence as a whole and the relative persuasiveness of the
arguments. See Id.; In re Hedges, 783 F.2d 1038, 1040, 228 USPQ
685, 687 (Fed. Cir. 1986); In re Piasecki, 745 F.2d 1468, 1472,
223 USPQ 785, 788 (Fed. Cir. 1984); and In re Rinehart, 531 F.2d
1048, 1051, 189 USPQ 143, 146-147 (CCPA 1976).
In the instant case, with regard to independent claim 1, the
examiner asserts that Yoshida shows, in Figure 3, a latch having
a hysteresis characteristic comprising an input buffer 200, a
data line D, a clock section 110, 90, 114, and a hysteresis latch
115-188, 103.
It is the examiner’s position that Yoshida shows the input
buffer as an inverter instead of a NAND gate enabled by an
enabling signal as required by the instant claims. However, the
examiner contends that Yoshida’s conventional CMOS inverter
buffer 200 is known to have a high power dissipation and that
Mote’s Figure 7 shows a NAND logic gate having an enable signal
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