Appeal No. 2003-0142
Application No. 09/071,912
claims, e.g., “configured so that said receiver enable input pin
(E) is settable to a high (Data ON) or low (Data OFF) voltage
level to set the hysteresis for the receiver latch circuit
section and also to gate any input data at a data input pad (D)
to the data line setting the hysteresis of the receiver latch
circuit section when the voltage level at said enable input pin
(E) goes high . . .” The examiner does not explain, in the
statement of the rejection and rationale therefor, how this
function would be accomplished by the attempted combination nor
does the examiner explain it in the response to appellants’
arguments, at pages 4-5 of the answer. Instead, the examiner
merely alleges, without support, that the combination of Yoshida
and Mote “has an input pin for receiving the inhibit signal
(enable signal) to set the hysteresis of the entire latch circuit
once it is in operation” (answer, page 4).
Accordingly, we find no prima facie case of obviousness
established by the examiner.
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