Appeal No. 2003-0142
Application No. 09/071,912
gate the input to the data line setting the hysteresis of the
receiver latch circuit section when the voltage goes high”
(brief, page 4, emphasis in original).
Appellants also point out that combining Yoshida with Mote
still does not provide for the missing elements of Yoshida
because Mote’s input buffer, as shown in Figure 7, is merely an
inverting input buffer and the substitution of one inverter (in
Yoshida) for another inverter (Mote’s Figure 7) does not result
in the instant claimed invention.
We agree with appellants.
It is not clear to us why one would take the inverting input
buffer of Mote and attempt to use it in the latching circuit of
Yoshida. But, even assuming the examiner’s rationale, i.e., the
reduction of power dissipation, would provide a motivation
(though there does not seem to be a power dissipation problem in
Yoshida) for making the combination, and, even if one were to
substitute Mote’s inverting input buffer, as shown in Figure 7,
for the inverter 200 of Yoshida, as the examiner attempts to do,
it is still not seen how this would result in a setting of the
hysteresis for a receiver latch circuit and also to gate any
input data, as specifically set forth in the instant claims.
The examiner does not address the specific limitations of the
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