Appeal No. 2003-0142
Application No. 09/071,912
for preventing the power supply connected to the system ground,
thus dissipating less power than the conventional CMOS inverter
buffer.
The examiner concludes, from this, that it would have been
obvious to replace Yoshida’s input buffer with Mote’s logic NAND
gate as an input buffer having the capability of enabling the
output signal, thus reducing power dissipation, as taught by Mote
(answer, pages 3-4).
Appellants take a different view. In particular, appellants
argue that the instant claimed invention allows voltage at a
receiver enable pin to set the hysteresis. This is said to be
recited by the instant claims by the inclusion of a “receiver
latch circuit section including a receiver feed section (20, 115,
119, 120), a clock section (30) and a hysteresis latch (40, 114,
114', 114", 116, 116', 116", 117, 118) having a pass gate (114).”
It is appellants’ position that the “receiver latch circuit
section,” as recited, distinguishes over the applied references
“because these elements are not in any reference as one combined
active section in which the entire receiver latch circuit section
is configured so that said receiver enable input pin (E) is
settable to a high (Data ON) or low (Data OFF) voltage level to
set the hysteresis for the receiver latch circuit section and to
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