Ex Parte KURIBAYASHI et al - Page 4




                Appeal No. 2003-0487                                                                                                    
                Application No. 09/158,925                                                                                              

                        [N]either Fig. 6 nor the rest of the Iwanaga reference teaches or suggests                                      
                        a system where a phase detector (or phase detecting means) detects a                                            
                        phase error “based on” or “existing in” a crosstalk-removed reading                                             
                        sample value sequence, as required by independent claims 1, 4, 7, 10, or                                        
                        13-14, respectively.                                                                                            
                The examiner responds to this argument on page 5 of the answer stating that figure 6 of                                 
                Iwanaga teaches a crosstalk extracting circuit and:                                                                     
                        Hence, by use of the cross talk extracting ability and provision thereof to                                     
                        an error extracting circuitry, the operation of this circuit parallels that of                                  
                        appellants’ figure 4.  Therefore, the examiner concludes errors (phase)                                         
                        either exists [sic, exist] or is [sic, are] present and modification of the                                     
                        acknowledged prior art figure 1 would lead to the claimed invention.                                            
                Further, on page 6 of the answer the examiner argues:                                                                   
                        With respect to the argument(s) presented that even if the above                                                
                        teachings one would still not be able to modify the primary reference in                                        
                        order to meet the claimed limitations, the examiner concludes that once                                         
                        the problem – crosstalk is recognized by the secondary reference, the                                           
                        positioning/placing of the appropriate element(s) to correct for such as                                        
                        close as possible to the source so as to mitigate against any negative                                          
                        impact on down stream circuits/processing is sufficient motivation to                                           
                        modify the primary reference and meet the claimed limitations.                                                  
                        We are unclear as to whether the examiner, by analogizing Iwanaga’s figure 6                                    
                with appellants figure 4, is arguing that Iwanaga teaches the limitation of a phase                                     
                detector, the output of which is used to generate a clock, or that the combination of the                               
                references teaches this limitation.  Regardless, we do not find that Iwanaga teaches or                                 
                suggests a phase determination circuit (or means) that detects a phase error in a cross                                 
                talk removed signal, and that the phase error is used to generate a clock.3                                             


                                                                                                                                        
                3 We note that the claimed phase error circuit is shown in appellants’ figure 2.                                        
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