Appeal No. 2003-0487
Application No. 09/158,925
art does not recognize the problem of crosstalk and Iwanaga does not identify an impact
of crosstalk on the clock. The only teaching we find in Iwanaga that addresses the
relation between the clock and crosstalk is on page 6 of the translation which identifies
that the crosstalk removal circuit’s effectiveness is reduced if the clock operates at the
bit rate. To prevent this reduction in effectiveness, Iwanaga teaches that the clock
should operate at twice the bit rate. Thus, we do not find that either of the references
provides a teaching or suggestion to use a phase detector, which detects a phase error
in a cross-talk removed sample value sequence, and a clock signal is generated based
upon this error. Accordingly, we will not sustain the rejection of claims 1 through 14
under 35 U.S.C § 103.
We next consider the rejections of claims 1 through 14 under 35 U.S.C § 102.
Appellants argue on pages 18 and 19 of the brief that Hayashi does not disclose a
phase detecting circuit that detects phase errors in a crosstalk removed sample value
sequence, and a clock signal is generated based upon this error. Appellants point out
that Hayashi does teach in the embodiment of figure 3 a circuit that produces a cross-
talk removed signal SB. However, appellants assert that “the crosstalk-removed reading
signal SB is not used by a subsequent phase detecting circuit to detect a phase error in
the reading signal in the manner required by appellants’ claims” (page 19 of brief).
Further, on page 20 of the brief, appellants argue that the embodiment shown in figure 9
of Hayashi “does not disclose a phase detecting circuit (or phase detecting means)
which detects a phase error ‘based on’ or ‘existing in’ the ‘crosstalk-removed reading
sample value sequence,’ as recited.”
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