Appeal No. 2003-0487
Application No. 09/158,925
Before we further discuss the teachings of the reference we must first determine
the scope of the claims. We find that the scope of each of the independent claims
includes a phase detector, which detects a phase error in a cross talk removed sample
value sequence, and a clock signal is generated based upon this error. See the
following limitations of claims 1 and 4: “a phase detecting circuit which detects a phase
error existing in the reading signal based on the crosstalk removed reading sample
value sequence; and a clock signal generating circuit which generates the clock signal
based on the phase error.” See also the following limitations of claims 7 and 10: “phase
detecting means for detecting a phase error existing in the reading signal based on the
crosstalk removed reading sample value sequence; and clock signal generating means
for generating the clock signal based on the phase error.” See the following limitations
of claim 13: “ a phase detecting circuit which detects a phase error existing in the
crosstalk-removed reading sample value sequence; and a clock signal generating circuit
which generates the clock signal based on the detected phase error.” Finally, see the
following limitations of claim 14 “ phase detecting circuit detects a phase error existing
in the crosstalk-removed reading sample value sequence and produces a detected
phase error at the output of the phase detecting circuit; and a clock signal generating
circuit having an input coupled to the output of the phase detecting circuit.
We do not find that Iwanaga, in figure 6 and the description of figure 6 on pages
6 though 8 of the translation, teaches that a phase determination circuit detects a phase
error in a crosstalk removed sample value sequence, and that the phase error is used to
generate a clock. While Iwanaga’s disclosure on page 6 of the translation states that
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